1. Field of the Invention
The invention relates generally to the field of nonvolatile memories (NVMs). More particularly, the invention relates to embedded NVMs. Specifically, a preferred implementation of the invention relates to trimming reference circuits for use in any NVM product, including stand alone and embedded NVMs.
2. Discussion of the Related Art
A reference circuit is typically used as a reference against which the performance of other circuits may be measured. In NVMs, the reference circuit typically needs to be calibrated to appropriate threshold voltages before it may be used.
Conventional embedded threshold voltage reference bits are typically trimmed to their desired value by a manual method. This manual method requires a tester for the chip first to program the bit, typically using an externally-timed program mode. The tester then reads the bit""s threshold voltage using a threshold voltage read mode. If the threshold voltage is too high, the tester applies an erase pulse, typically using an externally-timed erase mode. The tester then continues the process of reading the threshold voltage and erasing until the threshold voltage reaches the desired value.
To test a flash EEPROM, a tester provides a constant current through a device pin, and logic external to the NVM module will trim the reference cells to the correct target voltage range, as determined by the manufacturer. For NVM products, a reference circuit must be trimmed to the correct threshold voltage such that all operations (read, program, erase, etc) work correctly. Current methodology requires the tester to measure current through a high precision Parametric Measurement Unit (PMU), make decisions on whether to apply program or erase pulses, and apply the program or erase pulses until the PMU measures a current within the target range.
Currently, automated flash EEPROM array reference circuit trimming utilizes complicated external voltage, current measurements, and timing control mechanisms that are supported by using production test platforms. The process requires synchronization of DUTs (Devices Under Test) that are being tested, which in itself utilizes complex control software that is run on intelligent test platforms. These intelligent test platforms may automate the process, but the platforms require complex hardware and software to use. They typically use high precision power supplies and PMUs. Due to the time needed to calibrate each reference circuit, this entire process results in long test times, long resolution times to synchronize high precision supplies and PMUs, and may only allow a limited number of DUTs to be tested in parallel due to tester hardware limitations in parts such as the power supplies and PMUs.
Accordingly, the need for a simple and inexpensive test and trim tool for NVM reference circuits has not been fully met. The current testing tools on the market require complex and expensive software and testing equipment and take a long time to accomplish their task, resulting in lost time. There is a need for a solution that will quickly and simply test and debug NVM reference circuits.